1. Field of the Invention
The present invention relates generally to semiconductor memory devices, and more particularly, to a semiconductor memory device having a memory array divided into a plurality of memory blocks. More specifically, the present invention relates to a redundancy circuit for repairing a defective memory cell in a semiconductor memory device having such an array-divided arrangement and a power supply circuit provided corresponding to each block.
2. Description of the Background Art
In the semiconductor memory device, a defective memory cell is replaced with a spare memory cell in order to equivalently repair the defective memory cell to raise the yield of the products. A flexible redundancy scheme has been proposed in order to improve the use efficiencies of spare lines (word lines or bit lines) and spare decoders for selecting spare lines in a redundancy circuit configuration including spare memory cells (spare word lines and bit lines) for repairing such defective memory cells (see, for example, "A Flexible Redundancy Technique for High-Density DRAM's", Horiguchi et al., IEEE Journal of Solid-State Circuits, Vol. 26, No. 1, January 1991, pp. 12 to 17).
FIG. 53 is a schematic diagram of the general configuration of a semiconductor memory device having a conventional flexible redundancy scheme. In FIG. 53, the semiconductor memory device includes four memory arrays MA0 to MA3. In each of memory arrays MA0 to MA3, a spare word line to repair a defective memory cell row is provided. In memory array MA0, spare word lines SW00 and SW01 are provided, and in memory array MA1, spare word lines SW11 and SW11 are provided. In memory array MA2, spare word line SW20 and SW21 are provided, and in memory array MA3, spare word lines SW30 and SW31 are provided.
Row decoders X0 to X3 each for decoding an address signal to drive a normal word line provided corresponding to an addressed row into a selected state are provided corresponding to memory arrays MA0 to MA3. A column decoder Y0 is provided between memory arrays MA0 and MA1 to decode a column address signal to select an addressed column, and also a column decoder Y1 is provided between memory arrays MA2 and MA3.
The semiconductor memory device further includes spare decoders SD0 to SD3 to store a row address at which a defective memory cell is present, maintain a word line (defective normal word line) corresponding to this defective row address in a non-selected state when the defective row is addressed and drive a corresponding spare word line into a selected state, an OR circuit G0 to receive output signals from spare decoders SD0 and SD1, and an OR circuit G1 to receive output signals from spare decoders SD2 and SD3.
The output signals of OR circuits G0 and G1 are provided in common to spare word line driving circuits included in row decoders X0 to X3. Spare decoders SD0 to SD3 are commonly provided with array address signal bits an-2 and an-1 to address one of memory arrays MA0 to MA3 and with intra-array address signals bits a0 to an-3 to address a row in the memory array. Row decoders X0 to X3 are provided with array address signal bits an-2 and an-1, and a row decoder is activated when a corresponding memory array is addressed. OR circuits G0 and G1 each correspond to two spare word lines provided for each of memory arrays MA0 to MA3.
Let us assume that normal word lines W0 and W1 are defective in memory array MA0, that a normal word line W2 in memory array MA1 is defective, and that a normal word line W3 in memory array MA2 is defective. In this state, the address of word line W0 is programmed in spare decoder SD0, while the address of word line W1 is programmed in spare decoder SD2. The address of normal word line W2 is programmed in spare decoder SD3, and the address of normal word line W3 is programmed in spare decoder SD1.
OR circuit G0 selects one of spare word lines SW00, SW10, SW20 and SW30, and the output signal of OR circuit G1 selects one of spare word lines SW01, SW11, SW21 and SW31.
When normal word line W0 is addressed, the output signal of spare decoder SD0 is driven into a selected state, and the output of OR circuit G0 is activated. In this state, array address signal bits an-2 and an-1 activate row decoder X0, and the remaining row decoders X1 to X3 are maintained in a non-active state. Thus, a word line driving circuit included in row decoder X0 drives spare word line SW00 into a selected state in response to the output signal of OR circuit G0. At this time, in row decoder X0, a decode circuit provided corresponding to normal word line W0 is maintained in a non-active state. As a result, defective normal word line W0 is replaced with spare word line SW00.
If defective normal word line W1 is addressed, the output signal of spare decoder SD2 attains an H level in a selected state, the output signal of OR circuit G1 attains an H level, and spare word line SW01 is selected. If defective normal word line W2 is addressed, the output signal of spare decoder SD3 attains an H level in a selected state, the output signal of OR circuit G1 attains an H level, and spare word line SW11 is selected. If defective normal word line W3 is addressed, the output signal of spare decoder SD1 attains an H level in a selected state, and spare word line SW20 is selected by OR circuit G0 accordingly. More specifically, defective normal word lines W0, W1, W2 and W3 are replaced with spare word lines SW00, SW01, SW11 and SW20, respectively.
In this flexible redundancy scheme shown in FIG. 53, a single spare word line can be activated by any of a plurality of spare decoders. For example, spare word line SW20 can be driven into a selected state by spare decoder SD0 or SD1. A single spare decoder can drive any of a plurality of spare word line into a selected state. For example, spare decoder SD0 can drive any of spare word lines SW00, SW10, SW20 and SW30 into a selected state. Thus, the spare word line and spare decoders do not correspond in one-to-one relation, and therefore the spare word lines and spare decoders can be more efficiently utilized. The number of spare word lines and the number of spare row decoders in a single memory array may be selected independently from each other as long as the numbers satisfy the following relation: EQU L.ltoreq.R.ltoreq.M.multidot.L/m
wherein M is the number of physical memory arrays, m the number of memory arrays whose defective normal word lines are replaced with spare word lines simultaneously, R the number of spare row decoders, and L the number of spare word lines in a single memory array. More specifically, M/m is the number of memory arrays which are logically independent from one another. As a result, M.multidot.L/m represents the number of spare word lines which are logically independent from one another for the entire memory. Herein, the logically independent spare word lines are spare word lines selected by different row addresses. For example, in FIG. 53, if a normal word line is simultaneously selected in memory arrays MA0 and MA2, memory arrays MA0 and MA2 are not logically independent from each other. In the arrangement shown in FIG. 53, L=2, R=4, M=4 and m=1.
By providing a spare row decoder common to memory arrays, a spare decoder does not have to be provided for each of spare word lines, which can restrain the chip area from increasing.
The flexible redundancy scheme shown in FIG. 53 may be employed for repairing a defective column as well. In repairing a defective column, the previously mentioned prior art document describes a method of repairing a defective column where a memory array is divided into a plurality of sub-arrays. The document particularly describes the way of repairing a defective column in multi-divided bit lines in a shared-sense amplifier arrangement and in a shared I/O scheme.
FIG. 54 is a schematic diagram of the configuration of an array portion in a semiconductor memory device according to a conventional flexible redundancy scheme. In FIG. 54, two memory blocks MBi and MBi+1 are shown. Memory blocks MBi and MBi+1 each include a normal bit line pair BL and /BL provided corresponding to each memory cell column and a spare bit line (spare column) for repairing a defective column. In FIG. 54, the spare bit line included in the spare column is not clearly shown.
Normal bit lines BL and /BL at the same column address in memory blocks MBi and MBi+1 share a sense amplifier SA. A bit line isolation gate ILG is provided between sense amplifier SA and memory blocks MBi and MBi+1. Sense amplifier SA is connected to an internal data line pair I/O through an IO gate IOG which conducts in response to a column selecting signal YS from column decoder Y. A memory block including a selected memory cell (MBi, for example) is connected to sense amplifier SA and data is read out therefrom. In this case, a non-selected memory block (MBi+1) is disconnected from sense amplifier SA.
In the above-described shared-sense amplifier arrangement, a defective column address must be programmed for each of defects in normal bit lines, in a single memory block column selecting lines (YS lines) and sense amplifiers SA. For a normal bit line defect, the defective column address is programmed on a memory block basis. For a sense amplifier defect, the defective column address is so programmed as to use a spare column for each of memory blocks MBi and MBi+1 which share this defective sense amplifier. For a column selecting line (YS line) defect, the defective column address is programmed for each of the memory blocks connected to this column selecting line (YS line).
At the time of programming, in order to use a single spare column decoder for a normal bit line defect, a sense amplifier defect and a column selecting line (YS line) defect, "Don't care" is programmed at the time of programming a defective column address, an address to specify a memory block is invalidated, and spare columns are replaced simultaneously in a plurality of memory blocks.
In the previously mentioned document, a defective row is repaired by replacing the defective row with a spare word line provided within a memory array including that defective row. Thus, a spare word line must be provided for each of memory arrays, and the spare word lines are not efficiently utilized. If a defective normal word line in one memory array is replaced with a spare word line in another memory array, the control of the memory array related circuits will be complicated, and therefore such arrangement must be avoided and is not considered at all.
In repairing a defective column, a spare column is provided for each of memory blocks, and spare columns are similarly not efficiently used. Although the shared I/O scheme has been considered for internal data line arrangement, the way to repair a defective column in a memory array having a local/global hierarchical data line arrangement used in a recent block-divided arrangement has never been considered.
Meanwhile, in a conventional CMOS (Complimentary MOS) type semiconductor device, the size of components (MOS transistor: insulated gate type field effect transistor) is reduced to increase the integration density. In order to secure the reliability of the components thus miniaturized and to reduce the current consumed by the entire device, the power supply voltage is reduced. In order to allow the components to operate at a high speed, the threshold voltage of the MOS transistor must be lowered depending upon the power supply voltage. This is because if the ratio of the threshold voltage to the power supply voltage is large, the transition timing of the MOS transistor to the on state is delayed. If, however, the absolute value of the threshold voltage is lowered, sub-threshold leakage current to flow through the source-drain region when the MOS transistor is turned off increases. This is for the following reason. The threshold voltage is defined as the gate-source voltage to allow a prescribed drain current to flow. In an n-channel MOS transistor, if the threshold voltage is lowered, the drain current-gate voltage characteristic curve shifts toward the negative direction. The sub-threshold current is represented by the current value when gate voltage Vgs in the characteristic curve is 0V, and therefore the sub-threshold current increases as the threshold voltage is lowered.
When the semiconductor device operates, the ambient temperature increases, and the absolute value of the threshold voltage of the MOS transistor is lowered, resulting in more serious sub-threshold current leakage. When this sub-threshold leakage current increases, the DC current of the entire large scale integrated circuit increases, and particularly in a dynamic type semiconductor memory device, the stand-by current (current consumed in a stand-by state) increases.
In order to reduce the sub-threshold leakage current, a multi-threshold-voltage CMOS arrangement is employed.
FIG. 55 is a diagram showing a conventional multi-threshold-voltage CMOS arrangement by way of illustration. In FIG. 55, there are provided a main power supply line 902 transmitting a power supply voltage Vcc, a sub-power supply line 904 coupled to main power supply line 902 through a p-channel MOS transistor 903, a main ground line 906 transmitting a ground voltage Vss, and a sub-ground line 908 coupled to main ground line 906 through an n-channel MOS transistor 907. MOS transistor 903 conducts when an activation signal /.phi.ACT is at an L level, while MOS transistor 907 conducts when an activation signal .phi.ACT is at an H level. MOS transistors 903 and 907 each have a relatively high threshold voltage (high-Vth). The internal circuit operates, with a voltage from one of power supply lines 902 and 904 and a voltage from one of ground lines 906 and 908 used as both operation power supply voltages. In FIG. 55, as the internal circuit, three-stage, cascaded inverter circuits 914a, 914b and 914c are shown. Inverter circuit 914a includes a p-channel MOS transistor PQ having a source coupled to main power supply line 902, and an n-channel MOS transistor NQ having a source coupled to ground line 908. An input signal IN is provided in common to the gates of MOS transistors PQ and NQ. Input signal IN is set to an L level in a stand-by cycle.
Inverter circuit 914b operates using voltages on sub-power supply line 904 and main ground line 906 as both operation power supply voltages. Inverter circuit 914c operates with voltages on main power supply line 902 and sub-ground line 908 as both operation power supply voltages. MOS transistors PQ and NQ in each of these inverter circuits 914a to 914c have the absolute values of the threshold voltages set sufficiently small (low-Vth). The operation of the circuit shown in FIG. 55 will be now described with reference to FIG. 56.
In a stand-by cycle, input signal IN is set to an L level. Control signal .phi.ACT is at an L level, and control signal /.phi.ACT is at an H level (Vcc level). In inverter circuit 914b, MOS transistor PQ turns on, the source and drain thereof are at the same voltage level, and therefore no current is allowed to flow. Meanwhile, MOS transistor NQ is provided with input signal IN at the ground voltage level at its gate and is in an off state. However, the sub threshold leakage current allowed to flow through MOS transistor 907 in an off state is sufficiently reduced, because the threshold voltage of the transistor 907 is high. As a result, the sub-threshold current is reduced even if the threshold voltage of MOS transistor NQ is small. The sub-threshold current allowed to flow through MOS transistor 907 causes the voltage level on sub-ground line 908 to be higher than the ground voltage level, so that the gate-source region of MOS transistor NQ in inverter circuit 914a is set to a reverse bias state, and its sub-threshold current is further reduced.
In inverter circuit 914b, the input signal is at an H level, and MOS transistor NQ is turned on, the source and drain thereof are at the same voltage level and therefore no sub threshold leakage current is generated. Meanwhile, p-channel MOS transistor PQ is provided with a signal at power supply voltage Vcc level at its gate to allow sub-threshold leakage current to flow. However, since MOS transistor 903 is in an off state and MOS transistor 903 is a high-Vth transistor, the sub-threshold leakage current is sufficiently restrained. Thus, the sub-threshold leakage current in inverter circuit 914b is restrained. The sub-threshold leakage current of MOS transistor 903 causes the voltage level of sub-power supply line 904 to be lower than power supply voltage Vcc, and the gate-source region of MOS transistor PQ is reversedly biased in inverter circuit 914b, the sub-threshold leakage current of which is further restrained. Similarly to inverter circuit 914a, the sub-threshold leakage current is restrained in inverter circuit 914c.
When an active cycle is started, control signal .phi.ACT attains an H level, control signal /.phi.ACT attains an L level, MOS transistors 903 and 907 are turned on, sub-power supply line 904 is coupled to main power supply line 902, and sub-ground line 908 is coupled to main ground line 906. Thus, these inverter circuits 914a to 914c are supplied with a current from a corresponding power supply line/ground line, their low-Vth transistors operate at a high speed, and their output signals are changed according to change in input signal IN.
In the power supply circuit arrangement as shown in FIG. 55, since the logical level of an input signal in a stand-by cycle is previously known, a connection path to a power source line is determined accordingly. If the logical state of input signal IN in a stand-by cycle is not predetermined, the logic gate is coupled to sub-power supply line 904 and sub-ground line 908.
As disclosed in Japanese Patent Laying-Open No. 6-232348, in a DRAM (Dynamic Random Access Memory), circuits having the same circuit configuration such as decode circuits and word line drive circuits are provided. As the storage capacity increases, the number of such circuits significantly increases. In repeating circuitry having repeatedly provided decode circuits and word line drive circuits, a prescribed number of particular circuits (addressed circuits) are selectively driven among the circuits having the same configuration in response to an address signal. If these circuits are formed by low-Vth transistors, the power supply circuit arrangement as shown in FIG. 55 (hierarchical power supply arrangement: sub-threshold leakage current reducing circuit) may be employed. In this case, as shown in FIG. 53, activation/inactivation of a power supply to a decoder or a word line driver must be controlled for each of the blocks (because a word line is selected on a block basis.) Control signals .phi.ACT and /.phi.ACT are activated when an active cycle is started. As a result, the number of circuits connected to sub-power supply line 904 or sub-ground line 908 increases, and as the parasitic capacitance increases, it takes longer time until sub-power supply line 904 and sub-ground line 908 are driven to prescribed voltage (Vcc and ground voltage Vss) levels and therefore the operation starting timings of the internal circuits should be delayed until these voltages becomes stable, which impedes high-speed accessing operations.
As previously described, when a defective row/column is repaired using a spare decoder, a row/column to be selected is determined after determining if a spare is to be used/not used. In this case, as shown in FIG. 53, if redundancy replacement is performed within the same block, a corresponding power supply circuit (a circuit transmitting any of the power supply voltage and ground voltage) can be selected in response to an address signal to control the connection. If, however, a spare row/column is used for repairing a defective cell in another memory block in the flexible redundancy arrangement, a memory block including a memory cell to be driven into a selected state must be specified according to a spare determination result, the power source voltage (power supply voltage and ground voltage) cannot be driven into a stable state at a high speed, and high speed accessing operations cannot be implemented.